Integrated circuit (IC) chips or modules are often connected to chip carriers, and sometimes directly to PC boards or cards, by what is commonly referred to as C4 (controlled-collapsed-chip-connection) or flip-chip attachment technology. Small solder bumps or balls are formed on an active surface of the chip. The chip is then turned over (hence the name "flip-chip") and placed on the carrier, board or other substrate to which it will be attached. The components are heated to cause the solder to reflow in a controlled collapse which completes electrical connections between the chip and substrate. This technology has numerous advantages, including compact connections, electrical performance and cost, that have made it one of the industry standards. There are certain disadvantages, however, that have prevented even wider adoption.
One of the more significant disadvantages results from differences in the coefficients of thermal expansion (CTE) of the chip and substrate. Common chip materials such as silicon, germanium and gallium arsenide usually have CTEs of about 3 to about 6 ppm/.degree. C. Organic chip carriers to which the chips are attached and organic printed circuit boards and cards, which are usually composites of organic dielectrics and metallic circuitry, tend to have CTEs between about 12 and about 20 ppm/.degree. C. As these components are heated and cooled the substrates expand and contract much more than the chips. With a simple chip to substrate connection, the strain from the unequal expansion is absorbed primarily by the soft solder. With repetitive thermal cycles, which are inescapable with many electronic components, the solder joints are likely to fail.
A conventional approach to this problem is to surround the solder joints with a dielectric underfill material that matches or approximates the CTE of the solder joints, which is typically about 22 to about 28 ppm/.degree. C. Typical underfill materials are epoxy-based anhydride systems. They are normally heavily filled with very small particles of materials such as silicon dioxide to produce the desired CTE. The filler also gives the underfill a high modulus (as used herein, the term "modulus" refers to the storage modulus) typically greater than about 2 GPa or about 300 ksi. The underfill bears most of the load resulting from the differential expansion of the chip and substrate, and reduces the strain on the solder joints. However, by restricting the differential expansion between the chip and substrate, the relatively strong coupling between the chip and carrier has a tendency to warp both the chip and carrier. This increases loads acting normal to the surface of the substrate to which to which the carrier is attached. For example, as the package cools after the carrier has been attached to a printed circuit board or card, typically with an array of solder balls on BGA, the chip and carrier have a tendency to bow upward in the middle, which generates a tensile load on the balls at the center of the array between the carrier and the board or card. This can lead to premature failure of the BGA.
There have been many attempts to mitigate these problems, including stiffeners with a desirable CTE and layers of compliant material within a multi-layer organic printed circuit board or card. Stiffeners are expensive, however, and compliant layers within a board introduce stress concentrations where plated through holes (PTHs) pass through them became of the shear deformation. Thus, the need for reliable and inexpensive ways to accommodate for differential thermal expansion between chips and circuitized organic substrate such as chip carriers and printed circuit boards remains.